Invention Grant
US09329933B2 Imminent read failure detection based upon changes in error voltage windows for NVM cells
有权
基于NVM单元的误差电压窗口的变化的即时读取故障检测
- Patent Title: Imminent read failure detection based upon changes in error voltage windows for NVM cells
- Patent Title (中): 基于NVM单元的误差电压窗口的变化的即时读取故障检测
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Application No.: US14262157Application Date: 2014-04-25
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Publication No.: US09329933B2Publication Date: 2016-05-03
- Inventor: Jon W. Weilemann, II , Richard K. Eguchi
- Applicant: Jon W. Weilemann, II , Richard K. Eguchi
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agency: Egan, Peterman, Enders & Huston LLP
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G06F11/10 ; G06F11/07 ; G06F11/00 ; G11C16/34 ; G11C29/42 ; G11C11/56

Abstract:
Methods and systems are disclosed for imminent read failure detection based upon changes in error voltage windows for non-volatile memory (NVM) cells. In certain embodiments, data stored within an array of NVM cells is checked at a first time using a diagnostic mode and high/low read voltage sweeps to determine a first error voltage window where high/low uncorrectable errors are detected. Stored data is then checked at a second time using the diagnostic mode and high/low read voltage sweeps to determine a second error voltage window where high/low uncorrectable errors are detected. The difference between the error voltage windows are then compared against a voltage difference threshold value to determine whether or not to indicate an imminent read failure condition. An address sequencer, error correction code (ECC) logic, and a bias generator can be used to implement the imminent failure detection.
Public/Granted literature
- US20150309858A1 Imminent Read Failure Detection Based Upon Changes In Error Voltage Windows For NVM Cells Public/Granted day:2015-10-29
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