Invention Grant
US09329933B2 Imminent read failure detection based upon changes in error voltage windows for NVM cells 有权
基于NVM单元的误差电压窗口的变化的即时读取故障检测

Imminent read failure detection based upon changes in error voltage windows for NVM cells
Abstract:
Methods and systems are disclosed for imminent read failure detection based upon changes in error voltage windows for non-volatile memory (NVM) cells. In certain embodiments, data stored within an array of NVM cells is checked at a first time using a diagnostic mode and high/low read voltage sweeps to determine a first error voltage window where high/low uncorrectable errors are detected. Stored data is then checked at a second time using the diagnostic mode and high/low read voltage sweeps to determine a second error voltage window where high/low uncorrectable errors are detected. The difference between the error voltage windows are then compared against a voltage difference threshold value to determine whether or not to indicate an imminent read failure condition. An address sequencer, error correction code (ECC) logic, and a bias generator can be used to implement the imminent failure detection.
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