Invention Grant
- Patent Title: Redundant execution for reliability in a super FMA ALU
- Patent Title (中): 在超级FMA ALU中冗余执行可靠性
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Application No.: US13732228Application Date: 2012-12-31
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Publication No.: US09329936B2Publication Date: 2016-05-03
- Inventor: Brian J. Hickman
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06F9/00
- IPC: G06F9/00 ; G06F11/00 ; G06F11/14 ; G06F11/16

Abstract:
A system, processor and method to increase computational reliability by using underutilized portions of a data path with a SuperFMA ALU. The method allows the reuse of underutilized hardware to implement spatial redundancy by using detection during the dispatch stage to determine if the operation may be executed by redundant hardware in the ALU. During execution, if determination is made that the correct conditions exists as determined by the redundant execution modes, the SuperFMA ALU performs the operation with redundant execution and compares the results for a match in order to generate a computational result. The method to increase computational reliability by using redundant execution is advantageous because the hardware cost of adding support for redundant execution is low and the complexity of implementation of the disclosed method is minimal due to the reuse of existing hardware.
Public/Granted literature
- US20140189305A1 REDUNDANT EXECUTION FOR RELIABILITY IN A SUPER FMA ALU Public/Granted day:2014-07-03
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