A memory control circuit is configured to take a priority for each transfer instruction into account but not the priority in a memory access unit, and thus processing of a high-priority transfer instruction received during a memory access needs to wait for a long time. The memory control apparatus divides the received transfer instruction into a memory access unit and, when the transfer instruction having a higher priority is received during the memory access, the memory access based on a low-priority transfer instruction is interrupted and starts the memory access based on the high-priority transfer instruction.