Invention Grant
- Patent Title: Integrated circuit design synthesis using slack diagrams
- Patent Title (中): 集成电路设计综合使用松弛图
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Application No.: US14320589Application Date: 2014-06-30
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Publication No.: US09330216B2Publication Date: 2016-05-03
- Inventor: Mohit Parnami , Sorabh Sachdeva
- Applicant: Mohit Parnami , Sorabh Sachdeva
- Applicant Address: US TX Austin
- Assignee: FREESCALE SEMICONDUCTOR, INC.
- Current Assignee: FREESCALE SEMICONDUCTOR, INC.
- Current Assignee Address: US TX Austin
- Agent Charles E. Bergere
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
An updated integrated circuit (IC) design is generated by applying a histogram-based algorithm to an invalid, current IC design. The histogram-based algorithm includes worst negative slack (WNS) optimization followed by total negative slack (TNS) optimization. WNS optimization uses the slack histogram for the current IC design to generate an invalid, but improved, intermediate IC design. TNS optimization uses the slack histogram of the intermediate IC design to generate the updated IC design.
Public/Granted literature
- US20150379175A1 IC DESIGN SYNTHESIS USING SLACK DIAGRAMS Public/Granted day:2015-12-31
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