A memory device including a ferroelectric memory array is described. In one embodiment, the ferroelectric memory array includes a user memory space. The memory device includes control logic configured to provide external read and write access for a host system to the user memory space upon authentication between the host system and the memory device. The host system accesses the user memory space and communicates with the control logic through address, data and control buses. The memory device further includes memory interface configured to interface between the address, data and control buses and the control logic, and through which the host system communicates with the control logic, and a cipher engine in communication with the control logic and the memory interface, the cipher engine comprising a random number generator and an encryption/decryption block. Other embodiments are also described.