A semiconductor memory device includes a memory cell array, a voltage generation circuit that generates a voltage applied to the memory cell array, the voltage generation circuit including a plurality of boosting circuits connected in series between an input terminal and an output terminal, and a switching circuit configured to short-circuit one or more of the boosting circuits to the input terminal, and a control circuit that controls a conduction state of the switching circuit to vary the number of boosting circuits that are driven to generate the voltage applied to the memory cell array.