Invention Grant
- Patent Title: Dynamic window to improve NAND endurance
- Patent Title (中): 动态窗口提高NAND耐久性
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Application No.: US13997212Application Date: 2011-12-29
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Publication No.: US09330784B2Publication Date: 2016-05-03
- Inventor: Kiran Pangal , Ravi J. Kumar
- Applicant: Kiran Pangal , Ravi J. Kumar
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alpine Technology Law Group LLC
- International Application: PCT/US2011/067810 WO 20111229
- International Announcement: WO2013/101043 WO 20130704
- Main IPC: G11C29/02
- IPC: G11C29/02 ; G11C29/50 ; G11C29/10 ; G11C29/04 ; G06F11/10 ; G11C16/00

Abstract:
Methods and apparatus to provide dynamic window to improve NAND (Not And) memory endurance are described. In one embodiment, a program-erase window associated with a NAND memory device is dynamically varied by starting with a higher erase verify (TEV) voltage and lowering the TEV voltage with subsequent cycles over a life of the NAND memory device based on a current cycle count value. Alternatively, the program-erase window is dynamically varied by starting with a higher erase verify (PV) voltage and erase verify (TEV) voltage and lowering the PV and TEV voltages with subsequent cycles over a life of the NAND memory device based on the current cycle count value. Other embodiments are also disclosed and claimed.
Public/Granted literature
- US20140082460A1 DYNAMIC WINDOW TO IMPROVE NAND ENDURANCE Public/Granted day:2014-03-20
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