Method for forming control gate salicide

Invention Grant

US09330924B2 Method for forming control gate salicide 有权

Title translation: 形成控制闸门自杀的方法

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Patent Title: Method for forming control gate salicide
Patent Title (中): 形成控制闸门自杀的方法
Application No.: US14846646

Application Date: 2015-09-04
Publication No.: US09330924B2

Publication Date: 2016-05-03
Inventor: Huanxin Liu
Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
Applicant Address: CN Shanghai
Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
Current Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
Current Assignee Address: CN Shanghai
Agency: Kilpatrick Townsend & Stockton LLP
Priority: CN201410519468 20140929
Main IPC: H01L21/4763
IPC: H01L21/4763 ; H01L21/28 ; H01L29/423

Method for forming control gate salicide

Abstract:

A method for forming a semiconductor device includes forming a conductive structure of a silicon material on a substrate and forming a planarized dielectric layer adjacent the conductive structure. The method also includes removing a portion of the dielectric layer to expose a top portion of the conductive structure and removing an outer portion of the exposed top portion of the conductive structure such that the top portion of the gate structure has a narrower width than the unexposed portion. The method further includes forming a metal layer over the exposed portion of the gate structure and a top surface of the dielectric layer, and forming a silicide layer over the top portion of the conductive structure. The width of the silicided top portion of the conductive structure is substantially the same as the width of the bottom portion of the conductive structure.

Abstract(Chinese):

一种形成半导体器件的方法包括在衬底上形成硅材料的导电结构，并在导电结构附近形成平坦化的电介质层。该方法还包括去除电介质层的一部分以暴露导电结构的顶部并去除导电结构的暴露的顶部的外部部分，使得栅极结构的顶部具有比未曝光的宽度更窄的宽度一部分。该方法还包括在栅极结构的暴露部分和电介质层的顶表面上形成金属层，并且在导电结构的顶部上形成硅化物层。导电结构的硅化物顶部的宽度与导电结构的底部的宽度基本相同。

Public/Granted literature

US20160093498A1 METHOD FOR FORMING CONTROL GATE SALICIDE Public/Granted day:2016-03-31

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/02	.半导体器件或其部件的制造或处理
H01L21/04	..至少具有一个跃变势垒或表面势垒的器件，例如PN结、耗尽层、载体集结层
H01L21/34	...具有H01L21/06，H01L21/16及H01L21/18各组不包含的或有或无杂质，例如掺杂材料的半导体的器件
H01L21/46	....用H01L21/36至H01L21/428各组不包含的方法或设备处理半导体材料的（在半导体材料上制作电极的入H01L21/44）
H01L21/461	.....改变半导体材料的表面物理特性或形状的，例如腐蚀、抛光、切割
H01L21/4763	......非绝缘层的沉积，例如绝缘层上的导电层、电阻层；这些层的后处理（电极的制造入H01L21/28）