Invention Grant
US09330938B2 Method of patterning dopant films in high-k dielectrics in a soft mask integration scheme
有权
在软掩模集成方案中在高k电介质中构图掺杂剂膜的方法
- Patent Title: Method of patterning dopant films in high-k dielectrics in a soft mask integration scheme
- Patent Title (中): 在软掩模集成方案中在高k电介质中构图掺杂剂膜的方法
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Application No.: US14340068Application Date: 2014-07-24
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Publication No.: US09330938B2Publication Date: 2016-05-03
- Inventor: Takashi Ando , Hemanth Jagannathan , Balaji Kannan , Siddarth A. Krishnan , Unoh Kwon , Rekha Rajaram
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent L. Jeffrey Kelly; Steven Meyers
- Main IPC: H01L21/76
- IPC: H01L21/76 ; H01L21/3213 ; H01L21/28 ; H01L21/321

Abstract:
A method of fabricating advanced node field effect transistors using a replacement metal gate process. The method includes dopant a high-k dielectric directly or indirectly by using layers composed of multi-layer thin film stacks, or in other embodiments, by a single blocking layer. By taking advantage of unexpected etch selectivity of the multi-layer stack or the controlled etch process of a single layer stack, etch damage to the high-k may be avoided and work function metal thicknesses can be tightly controlled which in turn allows field effect transistors with low Tinv (inverse of gate capacitance) mismatch.
Public/Granted literature
- US20160027664A1 METHOD OF PATTERNING DOPANT FILMS IN HIGH-K DIELECTRICS IN A SOFT MASK INTEGRATION SCHEME Public/Granted day:2016-01-28
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