Invention Grant
- Patent Title: Semiconductor device and method of forming through vias with reflowed conductive material
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Application No.: US13944783Application Date: 2013-07-17
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Publication No.: US09331002B2Publication Date: 2016-05-03
- Inventor: Reza A. Pagaila , Byung Tai Do , Linda Pei Ee Chua
- Applicant: STATS ChipPAC, Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC, Ltd.
- Current Assignee: STATS ChipPAC, Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L21/30
- IPC: H01L21/30 ; H01L23/48 ; H01L21/683 ; H01L23/31 ; H01L23/00 ; H01L25/065 ; H01L25/00 ; H01L21/50

Abstract:
A semiconductor device is made by providing a first semiconductor wafer having semiconductor die. A gap is made between the semiconductor die. An insulating material is deposited in the gap. A portion of the insulating material is removed to form a first through hole via (THV). A conductive lining is conformally deposited in the first THV. A solder material is disposed above the conductive lining of the first THV. A second semiconductor wafer having semiconductor die is disposed over the first wafer. A second THV is formed in a gap between the die of the second wafer. A conductive lining is conformally deposited in the second THV. A solder material is disposed above the second THV. The second THV is aligned to the first THV. The solder material is reflowed to form the conductive vias within the gap. The gap is singulated to separate the semiconductor die.
Public/Granted literature
- US20130299975A1 Semiconductor Device and Method of Forming Through Vias with Reflowed Conductive Material Public/Granted day:2013-11-14
Information query
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