Invention Grant
US09331048B2 Bonded stacked wafers and methods of electroplating bonded stacked wafers
有权
粘合的堆叠晶片和电镀粘合堆叠晶片的方法
- Patent Title: Bonded stacked wafers and methods of electroplating bonded stacked wafers
- Patent Title (中): 粘合的堆叠晶片和电镀粘合堆叠晶片的方法
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Application No.: US14605486Application Date: 2015-01-26
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Publication No.: US09331048B2Publication Date: 2016-05-03
- Inventor: Quanbo Zou , Uppili Sridhar , Amit S. Kelkar , Xuejun Ying
- Applicant: Maxim Integrated Products, Inc.
- Applicant Address: US CA San Jose
- Assignee: Maxim Integrated Products, Inc.
- Current Assignee: Maxim Integrated Products, Inc.
- Current Assignee Address: US CA San Jose
- Main IPC: H01L23/02
- IPC: H01L23/02 ; H01L23/48 ; H01L23/52 ; H01L29/40 ; H01L23/00 ; B81C3/00 ; C25D7/12 ; C25D17/00 ; H01L25/00

Abstract:
A method including: providing a first wafer stack; applying a first bonding layer on the first wafer stack; providing a second wafer stack, where the second wafer stack includes vias; and applying a second bonding layer to the second wafer stack. The vias extend through the second wafer stack and to the second bonding layer. The second bonding layer is bonded to the first bonding layer. A seed layer is applied on a side of the second wafer stack opposite the second bonding layer such that a material of the seed layer (i) contacts the vias, and (ii) extends over and past ends of the second wafer stack and onto the first bonding layer.
Public/Granted literature
- US20150132891A1 BONDED STACKED WAFERS AND METHODS OF ELECTROPLATING BONDED STACKED WAFERS Public/Granted day:2015-05-14
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