Invention Grant
- Patent Title: Wafer scale technique for interconnecting vertically stacked dies
- Patent Title (中): 用于互连垂直堆叠模具的晶圆刻度技术
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Application No.: US14354647Application Date: 2012-11-01
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Publication No.: US09331051B2Publication Date: 2016-05-03
- Inventor: Pinxiang Duan , Elbertus Smalbrugge , Oded Raz , Harmen Joseph Sebastiaan Dorren
- Applicant: Technische Universiteit Eindhoven
- Applicant Address: NL Eindhoven
- Assignee: Technische Universiteit Eindhoven
- Current Assignee: Technische Universiteit Eindhoven
- Current Assignee Address: NL Eindhoven
- Agency: Lumen Patent Firm
- International Application: PCT/EP2012/071653 WO 20121101
- International Announcement: WO2013/064592 WO 20130510
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L23/00 ; H01L25/065 ; H01L25/00

Abstract:
A method and device for interconnecting stacked die surfaces with electrically conductive traces is provided that includes bonding, using a first layer of a photoresist compound, a second die (2) on top of a first die (1), heating the first layer above a pyrolyzation point of the photoresist compound, where the photoresist compound transitions to a stable layer, depositing a second layer of the photoresist compound (PR), using lithography, from a top surface of the first die (1) to a top surface of the second die (2), heating the second photoresist compound layer to a liquid state, where the liquid photoresist compound forms a smooth convex bridge between the first die (1) top surface and the second die (2) top surface, and depositing an electrically conductive layer on the smooth convex bridge, where an electrically conductive trace is formed between the first die (1) top surface and the second die (2) top surface.
Public/Granted literature
- US20140300008A1 Wafer scale technique for interconnecting vertically stacked dies Public/Granted day:2014-10-09
Information query
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