Invention Grant
- Patent Title: Methods for forming contact landing regions in split-gate non-volatile memory (NVM) cell arrays
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Application No.: US14706130Application Date: 2015-05-07
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Publication No.: US09331092B2Publication Date: 2016-05-03
- Inventor: Jane A. Yater , Cheong Min Hong , Sung-Taeg Kang
- Applicant: Freescale Semiconductor, Inc.
- Applicant Address: US TX Austin
- Assignee: FREESCALE SEMICONDUCTOR, INC.
- Current Assignee: FREESCALE SEMICONDUCTOR, INC.
- Current Assignee Address: US TX Austin
- Main IPC: H01L29/788
- IPC: H01L29/788 ; H01L27/115 ; H01L29/423

Abstract:
Methods and related structures are disclosed for forming contact landing regions in split-gate NVM (non-volatile memory) systems. A dummy select gate structure is formed while also forming select gates for split-gate NVM cells. A control gate layer is formed over the select gates and the dummy select gate structure, as well as an intervening charge storage layer. The control gate material will fill in gaps between the select gate material and the dummy select gate material. A non-patterned spacer etch is then used to etch the control gate layer to form a contact landing region associated with the dummy select gate structure while also forming spacer control gates for the split-gate NVM cells. The disclosed embodiments provide improved (e.g., more planar) contact landing regions without requiring additional processing steps and without increasing the pitch of the resulting NVM cell array.
Public/Granted literature
- US20150236035A1 Methods For Forming Contact Landing Regions In Split-Gate Non-Volatile Memory (NVM) Cell Arrays Public/Granted day:2015-08-20
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