Invention Grant
US09331153B2 Methods and structures for forming microstrip transmission lines on thin silicon on insulator (SOI) wafers
有权
在薄绝缘体(SOI)晶片上形成微带传输线的方法和结构
- Patent Title: Methods and structures for forming microstrip transmission lines on thin silicon on insulator (SOI) wafers
- Patent Title (中): 在薄绝缘体(SOI)晶片上形成微带传输线的方法和结构
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Application No.: US14105497Application Date: 2013-12-13
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Publication No.: US09331153B2Publication Date: 2016-05-03
- Inventor: Jeffrey R. LaRoche
- Applicant: Raytheon Company
- Applicant Address: US MA Waltham
- Assignee: RAYTHEON COMPANY
- Current Assignee: RAYTHEON COMPANY
- Current Assignee Address: US MA Waltham
- Agency: Daly, Crowley, Mofford & Durkee, LLP
- Main IPC: H01L29/20
- IPC: H01L29/20 ; H01L21/02 ; H01L21/762 ; H01L21/768 ; H01L21/8258 ; H01L23/66 ; H01L21/683

Abstract:
A structure is provided having: (A) a first silicon layer and a first silicon dioxide layer over the first silicon layer; and (B) a second silicon layer and a second silicon dioxide layer over the second silicon layer; the first silicon dioxide layer bonded to the second silicon dioxide layer. An upper surface of the first silicon layer is polished to reduce its thickness. A III-V layer is grown on the upper surface of the thinned silicon layer. A III-V device is formed in the III-V layer together with a strip conductor connected to the formed. The second silicon layer, the second silicon dioxide layer and the first silicon dioxide layer are successively removed to expose a bottom surface of the first silicon layer. A ground plane conductor is formed on the exposed bottom surface, the strip conductor and the ground plane conductor providing a microstrip transmission line.
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