Invention Grant
- Patent Title: Source tip optimization for high voltage transistor devices which includes a P-body extension region
- Patent Title (中): 包括P体扩展区域的高压晶体管器件的源尖端优化
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Application No.: US14153602Application Date: 2014-01-13
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Publication No.: US09331195B2Publication Date: 2016-05-03
- Inventor: Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai , Chih-Chang Cheng , Ruey-Hsin Liu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/08 ; H01L29/66 ; H01L21/225 ; H01L21/265 ; H01L29/06 ; H01L29/10 ; H01L29/423

Abstract:
The present disclosure provides a method for fabricating a high-voltage semiconductor device. The method includes designating first, second, and third regions in a substrate. The first and second regions are regions where a source and a drain of the semiconductor device will be formed, respectively. The third region separates the first and second regions. The method further includes forming a slotted implant mask layer at least partially over the third region. The method also includes implanting dopants into the first, second, and third regions. The slotted implant mask layer protects portions of the third region therebelow during the implanting. The method further includes annealing the substrate in a manner to cause diffusion of the dopants in the third region.
Public/Granted literature
- US20140110782A1 Source Tip Optimization For High Voltage Transistor Devices Public/Granted day:2014-04-24
Information query
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