Invention Grant
- Patent Title: Amplifier circuit with improved slew rate
- Patent Title (中): 具有提高转换速率的放大器电路
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Application No.: US14191816Application Date: 2014-02-27
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Publication No.: US09331648B2Publication Date: 2016-05-03
- Inventor: Takashi Narita
- Applicant: Takashi Narita
- Main IPC: H03F3/45
- IPC: H03F3/45 ; H03F1/34 ; H03F3/68 ; H03F1/22 ; H03F1/14

Abstract:
An amplifier circuit for improved slew rate consists of three main sections, which are the common mode rejection stage, primary gain stage and the output stage. The main circuit is a modified version of the fully differential operational amplifier circuit. The modifications done to this said circuit, enhances impedance which results in improved slew rate. In addition to the modifications in the primary gain stage, there's a cascade configuration to prevent systematic offset. The common mode rejection stage is primarily used due to the narrow common mode input range resulting from the cascade configuration. Additionally, another primary gain stage is included in the design prior to the output, since the output from the primary gain stage is narrow. This structure results in producing an improved slew rate.
Public/Granted literature
- US20140240043A1 AMPLIFIER CIRCUIT WITH IMPROVED SLEW RATE Public/Granted day:2014-08-28
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