Invention Grant
- Patent Title: Low power clock gated flip-flops
- Patent Title (中): 低功率时钟门控触发器
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Application No.: US14481992Application Date: 2014-09-10
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Publication No.: US09331680B2Publication Date: 2016-05-03
- Inventor: Girishankar Gurumurthy , Mahesh Ramdas Vasishta
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent John R. Pessetto; Charles A. Brill; Frank D. Cimino
- Main IPC: H03K3/356
- IPC: H03K3/356 ; H03K3/3562 ; H03K3/012
Abstract:
A flip-flop that includes a multiplexer configured to generate a multiplexer output. The multiplexer output is generated in response to an input and a scan enable, and is given to a transmission gate. A master latch is coupled to the transmission gate and to a tri-state inverter. The master latch is configured to receive an output of the transmission gate. A slave latch is configured to receive an output of the tri-state inverter and the multiplexer output. A data inverter is coupled to the slave latch. The data inverter is configured to generate a flip-flop output. A half clock gating inverter is configured to generate an inverted clock input in response to a clock input and the multiplexer output.
Public/Granted literature
- US20150070063A1 LOW POWER CLOCK GATED FLIP-FLOPS Public/Granted day:2015-03-12
Information query
IPC分类:
