Invention Grant
- Patent Title: Method and apparatus for reducing power bouncing of integrated circuits
- Patent Title (中): 降低集成电路功率跳动的方法和装置
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Application No.: US14296503Application Date: 2014-06-05
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Publication No.: US09331686B2Publication Date: 2016-05-03
- Inventor: Chia-Liang (Leon) Lin
- Applicant: Realtek Semiconductor Corp.
- Applicant Address: TW Hsinchu
- Assignee: REALTEK SEMICONDUCTOR CORP.
- Current Assignee: REALTEK SEMICONDUCTOR CORP.
- Current Assignee Address: TW Hsinchu
- Agency: McClure, Qualey & Rodack, LLP
- Main IPC: G05F1/00
- IPC: G05F1/00 ; G05F3/02 ; H03K17/16

Abstract:
A circuit is provided having a core circuit for sinking a first current from a first internal power supply node, a power bouncing reduction circuit for receiving power from a second internal power supply node and sourcing a second current to the first internal power supply node in accordance with a change of voltage at the first internal power supply node, and a package for coupling the first internal power supply node and the second internal power supply node to a first external power supply node and a second external power supply node, respectively. A corresponding method is also provided.
Public/Granted literature
- US20150358017A1 METHOD AND APPARATUS FOR REDUCING POWER BOUNCING OF INTEGRATED CIRCUITS Public/Granted day:2015-12-10
Information query
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