A system that includes an interface, a processor; and a hardware accelerator. The hardware accelerator is arranged to perform, for each Zadoff-Chu sequence of at least a first sub-set of the set of Zadoff-Chu sequences, a first hardware accelerator set of operations that includes frequency to time domain conversion to provide third intermediate vector that is associated with the Zadoff-Chu sequence. The processor is arranged to complete the Zadoff-Chu sequence search in response to the third intermediate vector—whereas the hardware accelerator and the processor are arranged to partially search the same Zadoff-Chu sequence at different periods of time.