Invention Grant
US09331822B1 Clock and data recovery circuit and method for estimating jitter tolerance thereof
有权
时钟和数据恢复电路及估计其抖动容限的方法
- Patent Title: Clock and data recovery circuit and method for estimating jitter tolerance thereof
- Patent Title (中): 时钟和数据恢复电路及估计其抖动容限的方法
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Application No.: US14794786Application Date: 2015-07-08
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Publication No.: US09331822B1Publication Date: 2016-05-03
- Inventor: Soon-Jyh Chang , Yu-Po Cheng , Yen-Long Lee , Chung-Ming Huang
- Applicant: NCKU RESEARCH AND DEVELOPMENT FOUNDATION , HIMAX TECHNOLOGIES LIMITED
- Applicant Address: TW Tainan TW Tainan
- Assignee: NCKU RESEARCH AND DEVELOPMENT FOUNDATION,HIMAX TECHNOLOGIES LIMITED
- Current Assignee: NCKU RESEARCH AND DEVELOPMENT FOUNDATION,HIMAX TECHNOLOGIES LIMITED
- Current Assignee Address: TW Tainan TW Tainan
- Agency: CKC & Partners Co., Ltd.
- Main IPC: H03L7/08
- IPC: H03L7/08 ; H03L7/093 ; H04L1/20 ; H04L7/00 ; H04B1/16 ; H04B1/04
Abstract:
A clock and data recovery circuit and a method for estimating jitter tolerance thereof are provided. A first phase signal is generated by a phase detector, and a second phase signal is used to generate a clock signal. The second phase signal is set to be identical to the first phase signal during an operation mode. A counting is started and the first phase signal is inversed to generate the second phase signal during a test mode. Whether a data signal has an error is determined. The counting is stopped to generate a count value when determining that the data signal has the error during the test mode. A tracing speed is computed according to the count value and a predetermined unit interval.
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