According to one embodiment, in an AD conversion circuit of a single slope type, a counter is configured to count number of clocks, in a state where a potential level of a first slope voltage and a potential level of a second slope voltage concurrently change, until an output signal of either one of a first comparator and a second comparator is inverted. A reference counter is configured to constantly output a full count value. A generation circuit is configured to generate and output a digital value corresponding to a count value of the counter when an output signal of the first comparator is inverted, and to generate and output a digital value corresponding to a value obtained by subtracting a count value of the counter from the full count value of the reference counter when an output signal of the second comparator is inverted.