Invention Grant
- Patent Title: Flip chip bump array with superior signal performance
- Patent Title (中): 翻转芯片阵列具有卓越的信号性能
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Application No.: US12938196Application Date: 2010-11-02
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Publication No.: US09332629B2Publication Date: 2016-05-03
- Inventor: Jitesh Shah
- Applicant: Jitesh Shah
- Applicant Address: US CA San Jose
- Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
- Current Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
- Current Assignee Address: US CA San Jose
- Agency: Roeder & Broder LLP
- Main IPC: H01L23/488
- IPC: H01L23/488 ; H05K1/11 ; H05K1/02 ; H01L23/50 ; H01L23/528 ; H01L23/498 ; H05K3/34
Abstract:
An integrated circuit (342) that is electrically connected to a printed circuit board (246) with a package substrate (344) includes a circuit body (352), and a bump array (354) that electrically connects the circuit body (352) to the package substrate (244). The bump array (354) includes a first bump set (356) having a plurality of signal bumps (364) and a plurality of non-signal bumps (366) alternatingly interspersed and aligned along an axis. With the present design, the bump array (354) allows each signal bump (364) to be surrounded by a power bump (370) and a ground bump (368). The package substrate (344) includes (i) a package body (372); and (ii) a pin array (374) that includes a first pin set (376) that includes a plurality of signal pins (384) and a plurality of non-signal pins (386) alternatingly interspersed and aligned along an axis.
Public/Granted literature
- US20120104596A1 FLIP CHIP BUMP ARRAY WITH SUPERIOR SIGNAL PERFORMANCE Public/Granted day:2012-05-03
Information query
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