Invention Grant
US09335376B2 Test architecture for characterizing interconnects in stacked designs
有权
用于表征堆叠设计中的互连的测试架构
- Patent Title: Test architecture for characterizing interconnects in stacked designs
- Patent Title (中): 用于表征堆叠设计中的互连的测试架构
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Application No.: US14183305Application Date: 2014-02-18
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Publication No.: US09335376B2Publication Date: 2016-05-10
- Inventor: Wu-Tung Cheng , Ruifeng Guo , Yu Huang , Liyang Lai , Jing Ye , Yu Hu
- Applicant: Mentor Graphics Corporation
- Applicant Address: US OR Wilsonville
- Assignee: Mentor Graphics Corporation
- Current Assignee: Mentor Graphics Corporation
- Current Assignee Address: US OR Wilsonville
- Main IPC: G01R31/3185
- IPC: G01R31/3185
Abstract:
The disclosed ring-oscillator-based test architecture comprises a plurality of boundary scan cells coupled to a plurality of interconnects and control circuitry. Each of the plurality of boundary scan cells can be configured to operate as, based on control signals, a conventional boundary scan cell or any bit of an asynchronous counter. The control signals are supplied by the control circuitry.
Public/Granted literature
- US20140237310A1 Test Architecture for Characterizing Interconnects in Stacked Designs Public/Granted day:2014-08-21
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