Invention Grant
- Patent Title: Data structures for efficient tiled rendering
- Patent Title (中): 数据结构,用于高效的平铺渲染
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Application No.: US13967233Application Date: 2013-08-14
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Publication No.: US09336002B2Publication Date: 2016-05-10
- Inventor: Ziyad S. Hakura , Pierre Souillot , Cynthia Allison , Dale L. Kirkland
- Applicant: NVIDIA CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: NVIDIA Corporation
- Current Assignee: NVIDIA Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Artegis Law Group, LLP
- Main IPC: G06T1/60
- IPC: G06T1/60 ; G06F9/38 ; G06T15/00 ; G06T15/40 ; G06T1/20 ; G09G5/395 ; G09G5/00 ; G06T15/50 ; G06F12/08 ; G06F9/44 ; G06T15/80

Abstract:
One embodiment of the present invention includes a method for performing a multi-pass tiling test. The method includes combining a plurality of bounding boxes to generate a coarse bounding box. The method further includes identifying a first cache tile associated with a render surface and determining that the coarse bounding box intersects the first cache tile. The method further includes comparing each bounding box included in the plurality of bounding boxes against the first cache tile to determine that a first set of one or more bounding boxes included in the plurality of bounding boxes intersects the first cache tile. Finally, the method includes, for each bounding box included in the first set of one or more bounding boxes, processing one or more graphics primitives associated with the bounding box. One advantage of the disclosed technique is that the number of intersection calculations performed for each cache tile is reduced.
Public/Granted literature
- US20140118393A1 DATA STRUCTURES FOR EFFICIENT TILED RENDERING Public/Granted day:2014-05-01
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