Invention Grant
US09336148B2 Cache memory, cache memory control unit, and method of controlling the cache memory
有权
高速缓冲存储器,缓存存储器控制单元和控制高速缓冲存储器的方法
- Patent Title: Cache memory, cache memory control unit, and method of controlling the cache memory
- Patent Title (中): 高速缓冲存储器,缓存存储器控制单元和控制高速缓冲存储器的方法
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Application No.: US14205418Application Date: 2014-03-12
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Publication No.: US09336148B2Publication Date: 2016-05-10
- Inventor: Taichi Hirao
- Applicant: Sony Corporation
- Applicant Address: JP Tokyo
- Assignee: SONY CORPORATION
- Current Assignee: SONY CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Hazuki International, LLC
- Priority: JP2013-061360 20130325
- Main IPC: G06F13/00
- IPC: G06F13/00 ; G06F13/28 ; G06F12/08

Abstract:
A cache memory includes: a tag storage section in which one of a plurality of indexes, each index containing a plurality of tag addresses and one suspension-indicating section, is looked up by a first address portion of an accessed address; a data storage section; a tag control section configured to, when the suspension-indicating section contained in the looked-up index indicates suspension, allow access relevant to the accessed address to wait, and when the suspension-indicating section contained in the looked-up index indicates non-suspension, compare a second address portion different from the first address portion of the accessed address to each of the plurality of tag addresses contained in the looked-up index, and detects a tag address matched with the second address portion; and a data control section.
Public/Granted literature
- US20140289473A1 CACHE MEMORY, CACHE MEMORY CONTROL UNIT, AND METHOD OF CONTROLLING THE CACHE MEMORY Public/Granted day:2014-09-25
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