Invention Grant
- Patent Title: Erase algorithm for flash memory
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Application No.: US14789252Application Date: 2015-07-01
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Publication No.: US09336893B2Publication Date: 2016-05-10
- Inventor: Jong Sang Lee , Hounien Chen , Kyoung Chon Jin
- Applicant: Integrated Silicon Solution, Inc.
- Applicant Address: US CA Milpitas
- Assignee: Integrated Silicon Solution, Inc.
- Current Assignee: Integrated Silicon Solution, Inc.
- Current Assignee Address: US CA Milpitas
- Agency: Van Pelt, Yi & James LLP
- Main IPC: G11C11/34
- IPC: G11C11/34 ; G11C16/34 ; G11C16/08 ; G11C16/16

Abstract:
A non-volatile memory device includes a sector pass/fail indicator circuit configured to store a pass/fail indicator for each sector in a first block of memory cells. The pass/fail indicator has a first value indicating the respective sector has failed erase verification and has a second value indicating the respective sector has passed erase verification. The sector pass/fail indicator circuit set the respective pass/fail indicators to the second value for one or more sectors in the first block after the respective sectors pass erase verification following a previous block erase operation of the first block. The first block is subjected to subsequent block erase operation where only word lines associated with the sectors having a pass/fail indicator having the first value are biased to the first bias voltage level.
Public/Granted literature
- US20150380101A1 ERASE ALGORITHM FOR FLASH MEMORY Public/Granted day:2015-12-31
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