An electronic device includes a memory. The memory includes a first cell array including a plurality of flash memory cells, a first peripheral circuit suitable for controlling the first cell array, a second cell array including a plurality of variable resistance memory cells, and a second peripheral circuit suitable for controlling the second cell array. The first cell array, the first peripheral circuit, and the second peripheral circuit are formed at a first level over a surface of a semiconductor substrate, and the second cell array is disposed at a second level over the surface of a semiconductor substrate, the second level being higher than the first level. A portion of the second cell array overlaps in a plan view the second peripheral circuit and/or the first cell array.