Invention Grant
- Patent Title: Tucked active region without dummy poly for performance boost and variation reduction
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Application No.: US14820938Application Date: 2015-08-07
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Publication No.: US09337338B2Publication Date: 2016-05-10
- Inventor: Brian J. Greene , Yue Liang , Xiaojun Yu
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Main IPC: H01L21/338
- IPC: H01L21/338 ; H01L29/78 ; H01L21/28 ; H01L29/66 ; H01L29/165 ; H01L21/02 ; H01L21/762 ; H01L29/06

Abstract:
In one embodiment, a semiconductor device is provided that includes a semiconductor substrate including an active region and at least one trench isolation region at a perimeter of the active region, and a functional gate structure present on a portion of the active region of the semiconductor substrate. Embedded semiconductor regions are present in the active region of the semiconductor substrate on opposing sides of the portion of the active region that the functional gate structure is present on. A portion of the active region of the semiconductor substrate separates the outermost edge of the embedded semiconductor regions from the at least one isolation region. Methods of forming the aforementioned device are also provided.
Public/Granted literature
- US20150349089A1 TUCKED ACTIVE REGION WITHOUT DUMMY POLY FOR PERFORMANCE BOOST AND VARIATION REDUCTION Public/Granted day:2015-12-03
Information query
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