The present disclosure provides for semiconductor structures and methods for making semiconductor structures. In one embodiment, isolation regions are formed in a substrate, and wells are formed between the isolation regions. The wells include a first low voltage well and a second low voltage well in a logic region of the substrate, and a memory array well in an NVM region of the substrate. A first layer of oxide is formed over the first low voltage well and the memory array well, and a second layer of oxide is formed over the second low voltage well, the second layer being thinner than the first layer. Gates are formed over the wells, including a first gate over the first low voltage well, a second gate over the second low voltage well, and a memory cell gate over the memory array well. Source/drain extension regions are formed around the gates.