Invention Grant
US09349484B2 Sample-and-hold circuit for an interleaved analog-to-digital converter
有权
用于交错模数转换器的采样和保持电路
- Patent Title: Sample-and-hold circuit for an interleaved analog-to-digital converter
- Patent Title (中): 用于交错模数转换器的采样和保持电路
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Application No.: US14808267Application Date: 2015-07-24
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Publication No.: US09349484B2Publication Date: 2016-05-24
- Inventor: Bob Verbruggen , Kazuaki Deguchi , Jan Craninckx
- Applicant: IMEC VZW
- Applicant Address: BE Leuven
- Assignee: IMEC VZW
- Current Assignee: IMEC VZW
- Current Assignee Address: BE Leuven
- Agency: McDonnell Boehnen Hulbert & Berghoff LLP
- Priority: EP14178665 20140725
- Main IPC: H03M1/00
- IPC: H03M1/00 ; G11C27/02 ; H03M1/12

Abstract:
The present disclosure relates to a sample-and-hold circuit includes a transistor arranged for switching between a sample mode and a hold mode and a bootstrap circuit arranged for maintaining in the sample mode a voltage level between a source terminal and a gate terminal of the transistor independent of the voltage at the source terminal and arranged for switching off the transistor in the hold mode. The bootstrap circuit includes a bootstrap capacitance arranged for being precharged to a given voltage during the hold mode, the bootstrap capacitance being connected between the source terminal and the gate terminal during the sample mode. In one example, the bootstrap circuit comprises a switched capacitor charge pump for generating the given voltage.
Public/Granted literature
- US20160027528A1 Sample-and-Hold Circuit for an Interleaved Analog-to-Digital Converter Public/Granted day:2016-01-28
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