A memory device according to embodiments includes a cell array region. The cell array region comprises a plurality of transistors sharing a word line, a plurality of memory elements, and a plurality of first contacts configured to connect the plurality of transistors with the plurality of memory elements, respectively, and aligned with a pitch. The memory device further comprises a second contact positioned at the pitch, along an extension of a row of the plurality of first contacts, outside the cell array region, and configured to be in contact with the word line.