Disclosed is an array substrate including gate lines (210), data lines (220) formed on a base substrate and a plurality of pixel units defined by intersecting the gate lines (210) and the data lines (220). Each pixel unit includes a TFT. In an overlapping area between an active layer (230) and a source (240) of the TFT, the active layer (230) includes at least two first tabs (231) beyond a gate (260) of the TFT which are located on both sides of a central line of the active layer (230) parallel to the gate line (210) respectively and the two first tabs (231) have a same width in a direction of gate line (210). The above-mentioned array substrate can guarantee that the gate-source capacitance is substantially identical to a predesigned capacitance even if the active layer experiences misalignment while being manufactured, thereby decreasing the error of the common electrode voltage Vcom. Further disclosed is a display device including the above-mentioned array substrate.