Invention Grant
US09351407B1 Method for forming multilayer device having solder filled via connection
有权
用于形成具有通过连接填充的焊料的多层器件的方法
- Patent Title: Method for forming multilayer device having solder filled via connection
- Patent Title (中): 用于形成具有通过连接填充的焊料的多层器件的方法
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Application No.: US14591933Application Date: 2015-01-08
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Publication No.: US09351407B1Publication Date: 2016-05-24
- Inventor: Boon Yew Low
- Applicant: Boon Yew Low
- Applicant Address: US TX Austin
- Assignee: FREESCALE SEMICONDUCTOR, INC.
- Current Assignee: FREESCALE SEMICONDUCTOR, INC.
- Current Assignee Address: US TX Austin
- Agent Charles E. Bergere
- Main IPC: H01K3/10
- IPC: H01K3/10 ; H05K3/40 ; H05K1/02 ; H05K1/11 ; H05K3/46

Abstract:
A method of forming a multilayer device includes providing a core substrate having opposing first and second core surfaces and forming top and bottom inner conductive patterns on each of the first and second core surfaces, respectively. A first dielectric layer is formed on the first core surface, and the top inner conductive pattern. A second dielectric layer is formed on the second core surface, and the bottom inner conductive pattern. The first and second dielectric layers are laminated with top and bottom outer conductive layers, respectively. A first via is provided through the core substrate extending from the top outer conductive layer to the bottom outer conductive layer. The first via is filled with solder. Magnetic particles are attracted by a magnetic force into the first via.
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