Invention Grant
- Patent Title: Method and apparatus of a three dimensional integrated circuit
- Patent Title (中): 三维集成电路的方法和装置
-
Application No.: US14137679Application Date: 2013-12-20
-
Publication No.: US09355205B2Publication Date: 2016-05-31
- Inventor: Chi-Wen Chang , Hui Yu Lee , Ya Yun Liu , Jui-Feng Kuan , Yi-Kan Cheng
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H01L23/48 ; H01L25/065

Abstract:
An apparatus includes a first tier and a second tier. The second tier is above the first tier. The first tier includes a first cell. The second tier includes a second cell and a third cell. The third cell includes a first ILV to couple the first cell in the first tier to the second cell in the second tier. The third cell further includes a second ILV, the first ILV and the second ILV are extended along a first direction. The first tier further includes a fourth cell. The second tier further includes a fifth cell. The second ILV of the third cell is arranged to connect the fourth cell of the first tier with the fifth cell of the second tier. In some embodiments, the second tier further includes a spare cell including a spare ILV for ECO purpose.
Public/Granted literature
- US20150179568A1 Method and Apparatus of a Three Dimensional Integrated Circuit Public/Granted day:2015-06-25
Information query