The BIST circuit includes an address data converting circuit that receives the logical address signal, the logical data signal, and the logical expected value signal. The address data converting circuit converts the logical data according to a physical configuration in the memory so as to generate a physical data signal specifying physical data to be written into the memory. The address data converting circuit converts the logical address according to the physical configuration in the memory so as to generate a physical address signal specifying a physical address of the memory for the physical data. The address data converting circuit converts the logical expected value according to the physical configuration in the memory so as to generate a physical expected value signal specifying a physical expected value that is an expected value of read data of the memory for the physical data.