Invention Grant
- Patent Title: Dual trench isolation for CMOS with hybrid orientations
- Patent Title (中): 具有混合取向的CMOS的双沟槽隔离
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Application No.: US13349203Application Date: 2012-01-12
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Publication No.: US09355887B2Publication Date: 2016-05-31
- Inventor: Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
- Applicant: Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Main IPC: H01L21/70
- IPC: H01L21/70 ; H01L21/762
Abstract:
The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.
Public/Granted literature
- US20120104511A1 DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS Public/Granted day:2012-05-03
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