Invention Grant
US09356570B2 High speed, rail-to-rail CMOS differential input stage 有权
高速,轨至轨CMOS差分输入级

High speed, rail-to-rail CMOS differential input stage
Abstract:
An apparatus is provided, comprising a single-ended input stage with signals IN_P & IN_N as input and OUT_P & OUT_N as output, wherein the differential input controlled by transistors P1-3 and N1-N3; and a means for weighting (sizing) of transistor (P1 & P3) relative to P2 and (N1 & N3) relative to N2 defines the optimal operation mode.
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