Invention Grant
US09362007B2 Semiconductor memory device 有权
半导体存储器件

Semiconductor memory device
Abstract:
A data transfer unit includes a first page buffer to latch data of a normal bit line connected to a normal memory cell, a second page buffer to latch data of a parity bit line connected to a parity memory cell, and a third page buffer to be first replaced when the first page buffer is defective or when the second page buffer 102c is defective. An error code correction bus is connected to the first and second page buffers, and a data bus is connected to the first, second and third page buffers.
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