Invention Grant
- Patent Title: Self-aligned semiconductor fabrication with fosse features
- Patent Title (中): 具有fosse特征的自对准半导体制造
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Application No.: US14266878Application Date: 2014-05-01
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Publication No.: US09362169B2Publication Date: 2016-06-07
- Inventor: Shih-Ming Chang , Ken-Hsien Hsieh , Chih-Ming Lai , Ming-Feng Shieh , Ru-Gun Liu , Tsai-Sheng Gau
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/3213
- IPC: H01L21/3213 ; H01L21/311 ; H01L21/768

Abstract:
The present disclosure describes methods for transferring a desired layout into a target layer on a semiconductor substrate. An embodiment of the methods includes forming a first desired layout feature as a first line over the target layer; forming a spacer around the first line; depositing a spacer-surrounding material layer; removing the spacer to form a fosse pattern trench surrounding the first line; and transferring the fosse pattern trench into the target layer to form a fosse feature trench in the target layer, wherein the fosse feature trench surrounds a first portion of the target layer that is underneath a protection layer. In some embodiments, the method further includes patterning a second desired layout feature of the desired layout into the target layer wherein the fosse feature trench and the protection layer serve to self-align the second desired layout feature with the first portion of the target layer.
Public/Granted literature
- US20150318209A1 Self-Aligned Semiconductor Fabrication With Fosse Features Public/Granted day:2015-11-05
Information query
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