Invention Grant
- Patent Title: Topological insulator in IC with multiple conductor paths
- Patent Title (中): 具有多个导体路径的IC中的拓扑绝缘体
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Application No.: US14447499Application Date: 2014-07-30
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Publication No.: US09362227B2Publication Date: 2016-06-07
- Inventor: Shoucheng Zhang , Jing Wang
- Applicant: The Board of Trustees of the Leland Stanford Junior University
- Applicant Address: US CA Stanford
- Assignee: The Board of Trustees of the Leland Stanford Junior University
- Current Assignee: The Board of Trustees of the Leland Stanford Junior University
- Current Assignee Address: US CA Stanford
- Agency: Patent Law Group LLP
- Agent Brian D. Ogonowsky
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/532 ; H01L23/528

Abstract:
A topological insulator is grown on an IC wafer in a vacuum chamber as a thin film interconnect between two circuits in the IC communicating with each other. As the TI is being grown, magnetic doping of the various TI sub-layers is varied to create different edge states in the stack of sub-layers. The sub-edges conduct in parallel with virtually zero power dissipation. Conventional metal electrodes are formed on the IC wafer that electrically contact the four corners of the TI layer (including the side edges) to electrically connect a first circuit to a second circuit via the TI interconnect. The TI interconnect thus forms two independent conducting paths between the two circuits, with each path being formed of a plurality of sub-edges. This allows bi-direction communications without collisions. Since each electrode contacts many sub-edges in parallel, the overall contact resistance is extremely low.
Public/Granted literature
- US20160035674A1 AUTOBAHN INTERCONNECT IN IC WITH MULTIPLE CONDUCTION LANES Public/Granted day:2016-02-04
Information query
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