Invention Grant
US09362264B2 Semiconductor device comprising a plurality of cell arrays including a well potential supply region and adjacent dummy gates provided on a well region of a cell array
有权
包括多个单元阵列的半导体器件，所述多个单元阵列包括提供在单元阵列的阱区上的阱电位区和相邻的虚拟栅
- Patent Title: Semiconductor device comprising a plurality of cell arrays including a well potential supply region and adjacent dummy gates provided on a well region of a cell array
- Patent Title (中): 包括多个单元阵列的半导体器件，所述多个单元阵列包括提供在单元阵列的阱区上的阱电位区和相邻的虚拟栅
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Application No.: US14576158Application Date: 2014-12-18
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Publication No.: US09362264B2Publication Date: 2016-06-07
- Inventor: Masaki Tamaru , Kazuyuki Nakanishi , Hidetoshi Nishimura
- Applicant: PANASONIC CORPORATION
- Applicant Address: JP Kanagawa
- Assignee: SOCIONEXT INC.
- Current Assignee: SOCIONEXT INC.
- Current Assignee Address: JP Kanagawa
- Agency: McDermott Will & Emery LLP
- Priority: JP2009-294231 20091225
- Main IPC: H01L27/02
- IPC: H01L27/02 ; H01L27/092 ; H01L21/8238 ; H01L27/118
Abstract:
A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.
Public/Granted literature
- US20150102420A1 SEMICONDUCTOR DEVICE Public/Granted day:2015-04-16
Information query
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