Two-Port SRAM cells are described. In an embodiment, a cell includes first, second, and read-port pull-down, first and second pull-up, first, second, and read-port pass-gate transistors. Each transistor includes a first source/drain region in an active area, a channel extending above the active area, and a second source/drain region above the channel. First source/drain regions of pull-down transistors are electrically coupled through a first active area. First source/drain regions of pull-up transistors are electrically coupled through a second active area. A first gate electrode is around channels of the first pull-up, first pull-down, and read-port pull-down transistors. A second gate electrode is around the channels of the second pull-up and pull-down transistors. Second source/drain regions of the first pull-up, pull-down, and pass-gate transistors are electrically coupled to the second gate electrode. Second source/drain regions of the second pull-up, pull-down, and pass-gate transistors are electrically coupled to the first gate electrode.