Tuning gate lengths in semiconductor device structures

Invention Grant

US09362354B1 Tuning gate lengths in semiconductor device structures 有权

Title translation: 调整半导体器件结构中的栅极长度

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Patent Title: Tuning gate lengths in semiconductor device structures
Patent Title (中): 调整半导体器件结构中的栅极长度
Application No.: US14624864

Application Date: 2015-02-18
Publication No.: US09362354B1

Publication Date: 2016-06-07
Inventor: Josephine B. Chang , Michael A. Guillorn , Isaac Lauer , Jeffrey W. Sleight
Applicant: International Business Machines Corporation
Applicant Address: US NY Armonk
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Current Assignee Address: US NY Armonk
Agency: Cantor Colburn LLP
Agent Vazken Alexanian
Main IPC: H01L21/84
IPC: H01L21/84 ; H01L29/06 ; H01L21/02 ; H01L29/66 ; H01L29/41

Tuning gate lengths in semiconductor device structures

Abstract:

A method for tuning gate lengths in nanowire semiconductor device structures. The present invention tunes the gate length by having the suspension height of the nanowire channels altered. The first method alters the suspension height by offsetting the height of the nanowires while utilizing gates of similar tapered dimensions, such that the nanowires pass through the gate regions at different heights and result in different gate length nanowire transistor device structures. The second method alters the suspension height by offsetting the height of the steps that the gates of similar tapered dimensions are formed on, such that the nanowires pass through the gate regions at different heights, resulting in different gate length nanowire transistor device structures. Both methods facilitate a decrease in overall fabrication costs by allowing the same type of patterned gate stacks to be used in order to produce channels of various lengths.

Abstract(Chinese):

一种用于调谐纳米线半导体器件结构中的栅极长度的方法。本发明通过改变纳米线通道的悬挂高度来调整栅极长度。第一种方法通过在利用类似锥形尺寸的栅极的同时抵消纳米线的高度来改变悬挂高度，使得纳米线在不同高度上通过栅极区域并且产生不同的栅极长度纳米线晶体管器件结构。第二种方法通过抵消形成类似的锥形尺寸的栅极的台阶的高度来改变悬挂高度，使得纳米线在不同的高度处通过栅极区域，导致不同的栅极长度的纳米线晶体管器件结构。两种方法通过允许使用相同类型的图案化栅极叠层来产生各种长度的沟道，从而有助于降低整体制造成本。

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IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/84	.....衬底不是半导体的，例如绝缘体