Invention Grant
- Patent Title: Delay circuit
- Patent Title (中): 延时电路
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Application No.: US14644143Application Date: 2015-03-10
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Publication No.: US09362923B2Publication Date: 2016-06-07
- Inventor: Takayuki Mizogami , Masayuki Koizumi
- Applicant: Kabushiki Kaisha Toshiba
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: White & Case LLP
- Priority: JP2014-148174 20140718
- Main IPC: H03L7/06
- IPC: H03L7/06 ; H03L7/081

Abstract:
A delay circuit includes units each of which includes a first delay element having a first input node and a first output node, a second delay element having a second input node and a second output node, and a third delay element between the first and second delay elements. The first output node of a first unit of the units is connected to the first input node of a second unit of the units. The second input node of the first unit is connected to the second output node of the second unit. A signal on the first input node of the first delay element of the first unit is output from the second output node of the second delay element of the first unit through the third delay element of the second unit.
Public/Granted literature
- US20160020774A1 DELAY CIRCUIT Public/Granted day:2016-01-21
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