Provided is to secure a data-writing period to a source line and reduce the number of the IC chips used. N image data (e.g., three image data, RGB) are sequentially input to one input terminal. Three switches, three first memory elements, three transfer switches, three second memory elements, and three buffers are connected in parallel to the input terminal. The three switches are turned on respectively. RGB image data are held in the three respective first memory elements. In a selection period of a gate line of an (m−1)-th row, image data of an m-th row are written to the first memory elements. When the three transfer switches are turned on in a selection period of a gate line of an m-th row, the image data are transferred to and held in the second memory elements. Then, the image data are output to each source line through each buffer.