Invention Grant
US09368206B1 Capacitor arrangements using a resistive switching memory cell structure
有权
使用电阻式开关存储单元结构的电容器布置
- Patent Title: Capacitor arrangements using a resistive switching memory cell structure
- Patent Title (中): 使用电阻式开关存储单元结构的电容器布置
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Application No.: US14325119Application Date: 2014-07-07
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Publication No.: US09368206B1Publication Date: 2016-06-14
- Inventor: John Dinh , Ming Sang Kwan , Venkatesh P. Gopinath , Derric Lewis , Shane Hollmer , John R. Jameson , Michael Van Buskirk
- Applicant: Adesto Technologies Corporation
- Applicant Address: US CA Sunnyvale
- Assignee: Adesto Technologies Corporation
- Current Assignee: Adesto Technologies Corporation
- Current Assignee Address: US CA Sunnyvale
- Agent Michael C. Stephens, Jr.
- Main IPC: G11C13/00
- IPC: G11C13/00

Abstract:
In one embodiment, a capacitive circuit can include: (i) a resistive storage element having a solid electrolyte, a first electrode coupled to a first side of the solid electrolyte, and a second electrode coupled to a second side of the solid electrolyte; (ii) the resistive storage element being configured to be programmed to a low resistance state by application of a program voltage in a forward bias direction to form a conductive path between the first and second electrodes, and being configured to be erased to a high resistance state by application of an erase voltage in a reverse bias direction to substantially dissolve the conductive path; and (iii) a first capacitor having the first electrode coupled to a first side of a first oxide layer, and a third electrode coupled to a second side of the first oxide layer.
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