Invention Grant
US09368209B2 Embedded non-volatile memory with single polysilicon layer memory cells programmable through channel hot electrons and erasable through fowler-nordheim tunneling
有权
嵌入式非易失性存储器，单个多晶硅层存储单元可通过通道热电子编程，并可通过fowler-nordheim隧道进行擦除
- Patent Title: Embedded non-volatile memory with single polysilicon layer memory cells programmable through channel hot electrons and erasable through fowler-nordheim tunneling
- Patent Title (中): 嵌入式非易失性存储器，单个多晶硅层存储单元可通过通道热电子编程，并可通过fowler-nordheim隧道进行擦除
-
Application No.: US14605246Application Date: 2015-01-26
-
Publication No.: US09368209B2Publication Date: 2016-06-14
- Inventor: Luca Milani , Fabrizio Torricelli , Anna Richelli , Luigi Colalongo , Zsolt Miklos Kovàcs-Vajna
- Applicant: STMICROELECTRONICS S.R.L.
- Applicant Address: IT Agrate Brianza (MB)
- Assignee: STMICROELECTRONICS S.R.L.
- Current Assignee: STMICROELECTRONICS S.R.L.
- Current Assignee Address: IT Agrate Brianza (MB)
- Agency: Allen, Dyer, Doppelt, Milbrath & Gilchrist, P.A.
- Priority: ITMI2014A0156 20140220
- Main IPC: G11C16/10
- IPC: G11C16/10 ; G11C16/04 ; H01L27/115 ; H01L21/28 ; H01L29/66 ; H01L29/788
Abstract:
A non-volatile memory includes memory cells arranged in rows and columns. Each memory cell includes a program/read portion and an erase portion that share an electrically floating layer of conductive material defining a first capacitive coupling with the program/read portion and a second capacitive coupling with the erase portion. The first capacitive coupling defines a first capacitance greater than a second capacitance defined by the second capacitive coupling. The erase portion is configured so that an electric current extracts charge carriers from the electrically floating layer to store a first logic value in the memory cell. The program/read portion is further configured so that an electric current injects charge carriers in the electrically floating layer to store a second logic value in the memory cell.
Public/Granted literature
Information query
