A flash memory controller is configured to provide a first erase mode for erasing one or more groups of flash memory cells in a flash memory device using a plurality of erase pulses and a second erase mode for erasing the one or more groups of flash memory cells using a single erase pulse. The controller may receive a fast erase signal to erase the one or more groups of flash memory cells and, in response to the signal, switch operating parameters of the flash memory device from first parameters corresponding to the first erase mode to second parameters corresponding to the second erase mode, and instruct the flash memory device to perform an erase operation on the one or more groups of flash memory cells according to the second parameters. The controller may then verify that the erase operation was completed using the single erase pulse.