Invention Grant
- Patent Title: Manufacturing method for semiconductor integrated circuit device
- Patent Title (中): 半导体集成电路器件的制造方法
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Application No.: US13781737Application Date: 2013-02-28
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Publication No.: US09368385B2Publication Date: 2016-06-14
- Inventor: Akira Imai , Toshiaki Iwamatsu , Akihiro Nakae
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Shapiro, Gabor and Rosenberger, PLLC
- Priority: JP2012-045346 20120301
- Main IPC: H01L21/76
- IPC: H01L21/76 ; H01L21/68 ; H01L27/12 ; H01L23/544 ; H01L21/762 ; H01L21/3105
Abstract:
A method for manufacturing a semiconductor integrated circuit device includes the step of forming an SOI device region and a bulk device region on an SOI type semiconductor wafer. The method includes: removing a BOX layer and an SOI layer in a bulk device region; and thereafter forming an STI region in both the SOI device region and the bulk device region. In the method, the STI region in the SOI device region is formed to extend through the BOX layer.
Public/Granted literature
- US20130230964A1 MANUFACTURING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Public/Granted day:2013-09-05
Information query
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