Invention Grant
US09368624B2 Method for fabricating a transistor with reduced junction leakage current
有权
具有减小的结漏电流的晶体管的制造方法
- Patent Title: Method for fabricating a transistor with reduced junction leakage current
- Patent Title (中): 具有减小的结漏电流的晶体管的制造方法
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Application No.: US14808122Application Date: 2015-07-24
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Publication No.: US09368624B2Publication Date: 2016-06-14
- Inventor: Scott E. Thompson , Lucian Shifren , Pushkar Ranade , Yujie Liu , Sung Hwan Kim , Lingquan Wang , Dalong Zhao , Teymur Bakhishev , Thomas Hoffmann , Sameer Pradhan , Michael Duane
- Applicant: MIE Fujitsu Semiconductor Limited
- Applicant Address: JP Kuwana, Mie
- Assignee: Mie Fujitsu Semiconductor Limited
- Current Assignee: Mie Fujitsu Semiconductor Limited
- Current Assignee Address: JP Kuwana, Mie
- Agency: Baker Botts L.L.P.
- Main IPC: H01L21/331
- IPC: H01L21/331 ; H01L29/78 ; H01L29/66 ; H01L29/10 ; H01L29/08 ; H01L21/8238

Abstract:
A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.
Public/Granted literature
- US20150333144A1 High Uniformity Screen and Epitaxial Layers for CMOS Devices Public/Granted day:2015-11-19
Information query
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